Senior R&D Engineer
5 miesięcy temu
Description
:Our R&D engineers and scientists develop breakthrough technologies that change the way the world works, and industries do business. We constantly push the limits of convention, while retaining our focus on delivering quality products and solutions to our customers.
Over 60 years ago, Hitachi Energy introduced a new way of transmitting electricity across long distances with minimum losses – High Voltage Direct Current (HVDC). HVDC technology can now deliver up to 12 gigawatts of power at voltage levels of up to 1,100 kV, covering distances of more than 3,000 kilometres.
You will contribute significantly to successful results in the heart of HVDC station:Modular Advanced Control for HVDC (MACH™).The MACH™ control system provides unequalled calculation capacity and enables a high degree of integration and handling for all control and protection functions. Moreover, MACH™ control provides advanced fault registration and remote control functions. The system is designed to run 24/7 for thirty years or more, allowing the HVDC system to be controlled and protected in the most reliable way throughout its life time.
As a part of global R&D organization you will cooperate on daily bases with colleagues from MACH teams in Sweden and India. Development in Krakow covers DSP Control & Protection, I/O systems, Power Electronics units and robust communication. FPGA development is done on chips delivered by Xilinx, Lattice and Microsemi. Working under SAFe framework you will develop further your skills and contribute into development of next generations of MACH™ system. You are going to work in the team leaded by .
Your responsibilities:
Participation in full design cycle of next generation HVDC control and protection system based on FPGA modules from world class vendors. Scouting of applicable solutions based on project requirements, having real impact on requirements and final solution. Development, simulation, and validation using VHDL + ModelSim + VUnit. Contributing to continues integration process. Prototyping and testing on real HW in modern laboratories. Cooperation with international teams under Agile/SAFe methodology.Your background:
At least Master's degree in Electronics/Control Engineering or related field. Experience of FPGA/ASIC design & simulation in VHDL/(and/or Verilog) - 5 years for Senior, 5-10 for Senior II Good understanding of synchronous design, time constraining and static timing analysis. Experience with laboratory equipment, prototyping and testing. Strong commitment to safe work practices and dedication to following all relevant workplace safety guidelines. High level of self-motivation, curiosity, and desire to learn about modern technologies. A collaborative, solutions-oriented approach, and effective communication skills. Experience in modelling in High Level Synthesis would be an advantage. Experience in self-testing test-benches and regression tests would be an advantage.-
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