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Senior Analog IP Design Engineer
1 miesiąc temu
We are seeking an experienced Senior Analog IP Design Engineer to join our team in Warsaw, Poland.
About the RoleThe successful candidate will be responsible for developing and customizing analog IP blocks and subsystems, as well as architectural design of larger systems.
Key responsibilities include:
- Participating in spec definition and effort estimations
- Collaborating with layout teams on and offsite
- Producing and presenting design review documentation according to internal quality flows
To be considered for this role, you should have:
- 2 years of experience in analog IC design or a relevant suitable combination of education, training, and experience
- Knowledge of the CMOS IC development process
- Experience in designing high-speed SerDes, ADC and DAC, PLL, LDO, BandGap, Power Management, MIPI, and other Interface IPs
- Relevant experience in 40nm design or more advanced process nodes
- A strong understanding of design for mass production and test
As a Senior Analog IP Design Engineer at Cadence, you can expect:
- A competitive salary package
- Copyrights tax relief procedure implemented in salary calculations
- Flexible working hours
- Work from office or hybrid
- Continuous professional development: trainings and seminars
- Possibility to cooperate with people from around the world in an expanding global organization
We encourage you to apply if you are looking for continued professional development and want to create solutions that will influence the development of exciting new technology.
