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RTL Engineer Leader

1 tydzień temu

Warszawa, Mazovia, Polska Cadence Design Systems Pełny etat
Job Qualifications and Skills
  • Bachelor's or Master's degree in Electrical Engineering or Computer Science
  • Experience with RTL design, preferably with Verilog/System Verilog
  • Strong debugging and analytical skills
  • Digital architecture trade-offs for power, performance, and area
  • Ability to handle multiple asynchronous clock domains and their crossings (CDC)
  • Knowledge of UNIX/Linux, shells, programming, and scripting
  • Effective communication skills and ability to work remotely
  • Team player with fluent English skills
  • At least 2 years of applicable experience
  • Must be legally eligible to work in Poland