HW IP Design Engineer

4 dni temu

Gdańsk, Pomerania, Polska Intel GmbH Pełny etat
About the Role

We are looking for a highly skilled engineer to join our GPU Hardware IP Poland team, located in Katowice/Gdańsk. As a member of this team, you will be responsible for supporting technical leadership in HW IP verification and overall definition, design, implementation, and documentation for SoC sub-system development.

This role involves collaborating with teams of design engineers, system architects, micro-architects, and verification engineers to ensure that the design meets specifications. You will also be responsible for developing and implementing verification strategies and plans, and ensuring that the verification process is completed efficiently and effectively.

Responsibilities
  • Develop and implement verification strategies and plans.
  • Collaborate with teams of design engineers, system architects, micro-architects, and verification engineers to ensure that the design meets specifications.
  • Ensure that the verification process is completed efficiently and effectively.

Requirements

  • Candidate should possess a Master's and/or a PhD degree in Electronics, Electrical Engineering, or Computer Science Engineering.
  • 2+ years of ASIC design and verification industry experience in front end processes, including:
    • Extensive knowledge of Verilog and System Verilog and working knowledge of UVM methodology.
    • Good understanding of functional verification:
      • Experience in the full verification cycle from specification to silicon.
      • Experience in verification strategy and test planning, directed and stress test generation, good knowledge of functional and code coverage, verification infrastructures, and verification and/or debug flows.
      • Fundamentals of state machine verification.
      • Complex protocol verification.
    • Knowledge of co-simulation using SV/DPI or other tools.
    • Adept in programming and/or scripting (C++, Perl, and others) and conversant with flows and tools for VLSI logic design and/or functional verification.
    • Expertise in C/C++ modelling (best if using Algorithmic C / AC-types).
    • Expertise in synthesis flow and timing closure, and in multi-clock domain designs.
    • Functional and power/performance optimization and verification (experience in considerations for power, performance, and cost optimization is desirable).
    • Experience in Formal Verification:
      • Expert in SVA (SystemVerilog assertions).
      • Experience in Formal Verification: control and data path / FPV and DPV.
    • Experience in signal processing, DSP, algo development, and numerical validation.
    • Knowledge of digital electronics.
  • Experience in reading and writing technical documentation (high-level spec and micro-architecture spec is desirable).
  • Knowledge of CPU/GPU hardware architectures and components and GPU hardware pipeline.
  • Ability to work effectively with both internal and external teams and stakeholders, have strong problem-solving and good communication skills (English and Polish).

Nice to Have

  • Knowledge of 3D graphics theory, rendering algorithms, and techniques used in games.
  • Knowledge of SoC and Platform level product architectures.
  • Experience with Synopsys and Cadence tools.
  • Experience in mentoring junior engineers as well as the ability to drive more complex tasks.
  • Experience in multi-power domain / multi-clock domain designs and CDC.

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