Design Verification Engineer

5 dni temu

Kraków, Lesser Poland DCG Pełny etat 60 000 zł - 120 000 zł rocznie

As a recruitment company, DCG understands that every business is powered by experienced professionals. Our management style and partnership approach enable us to meet your needs and provide continuous support. Due to our ongoing growth and the large number of recruitment projects we undertake for our partners, we are currently looking for:

Design Verification Engineer

Responsibilities

  • Define, document, develop, and run simulation-based verification tests for the compiler tool, compatible with major RTL simulators (Cadence, Synopsys, Siemens).
  • Create and execute Python-based validation tests to qualify additional Register tool outputs (IP-XACT, C header files, documentation).
  • Maintain and improve tests within the continuous integration environment, enhancing automation and quality metrics.
  • Contribute to refining internal processes, methodologies, and performance indicators.
  • Work with modern documentation and project-tracking platforms (e.g., Confluence, Jira).
  • Work closely with developers to understand verification requirements and EDA-specific scenarios.
  • Participate in code reviews and support unit testing to ensure high code quality.

Requirements

  • At least 7 years of professional experience in RTL verification.
  • Strong command of the UVM methodology.
  • Solid knowledge of RTL design languages (VHDL, Verilog, SystemVerilog).
  • Strong Python skills for scripting and automation.
  • Bonus skills: familiarity with IP-XACT, C-HAL, and equivalence-checking tools.
  • Excellent communication skills in English.
  • Independent, detail-oriented, quality-focused, and proactive.
  • Degree in Computer Science, Electronics, or a related discipline.
  • Fluent in English.

Desirable:

  • Knowledge of French.

What We Offer

  • Private healthcare package
  • Lunch card

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