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Principal r&d engineer

4 miesięcy temu


Kraków, Lesser Poland Hitachi Vantara Corporation Pełny etat

Our R&D engineers and scientists create groundbreaking technologies that revolutionize the way the world operates, and industries conduct business.

We constantly challenge traditional boundaries, while maintaining our commitment to delivering top-notch products and solutions to our clients.

Over six decades ago, Hitachi Energy introduced an innovative method of transmitting electricity over long distances with minimal losses – High Voltage Direct Current (HVDC).

HVDC technology can now transport up to 12 gigawatts of power at voltage levels of up to 1,100 kV, spanning distances exceeding 3,000 kilometers.

You will play a significant role in driving successful outcomes at the core of the HVDC station: Modular Advanced Control for HVDC (MACH).

The MACH control system offers unparalleled computing capacity and facilitates seamless integration and management of all control and protection functions.

Furthermore, MACH control offers advanced fault detection and remote control capabilities.

The system is engineered to operate 24/7 for thirty years or more, ensuring the HVDC system is controlled and safeguarded in the most dependable manner throughout its lifespan.

As a member of the global R&D team, you will collaborate daily with MACH teams in Sweden and India.

Development activities in Krakow encompass DSP Control & Protection, I/O systems, Power Electronics units, and reliable communication. FPGA development is carried out using chips supplied by Xilinx, Lattice, and Microsemi.

Operating within the SAFe framework, you will enhance your skills and contribute to the advancement of future generations of the MACH system.

You will be part of the team led by Mateusz Guzik.



Your responsibilities:

  • Participation in the complete design cycle of the next generation HVDC control and protection system based on FPGA modules from leading vendors.
  • Exploration of viable solutions based on project needs, influencing requirements and the ultimate solution.
  • Development, simulation, and validation using VHDL + Model Sim + VUnit.
  • Contributing to continuous integration procedures.
  • Prototyping and testing on actual hardware in state-of-the-art laboratories.
  • Collaboration with international teams following Agile/SAFe methodologies.
  • Embodying Hitachi's core values of safety and integrity by taking accountability for your actions while looking out for your colleagues and the business.

Your background:

  • Minimum Master's degree in Electronics/Control Engineering or a related discipline.
  • At least 15 years of FPGA/ASIC design & simulation experience in VHDL/(and/or Verilog).
  • Solid grasp of synchronous design, time constraints, and static timing analysis.
  • Proficiency in laboratory equipment usage, prototyping, and testing.
  • Dedication to adhering to safe work practices and following all relevant workplace safety protocols.
  • High level of self-motivation, inquisitiveness, and eagerness to explore modern technologies.
  • A collaborative, solution-focused mindset, and effective communication abilities.
  • Experience in modeling in High-Level Synthesis would be advantageous.
  • Experience in self-testing test-benches and regression tests would be beneficial.